1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a metal oxide silicon field effect transistor (hereinafter "MOSFET") for a semiconductor memory device and fabrication method of same.
2. Background of the Related Art
As shown in FIG. 1, a conventional MOSFET has an active region 1a and a field region 1b. The MOSFET includes a semiconductor substrate 1 defining a source 2 and a drain 3 in the active region 1a. A gate insulation layer 4 and a field insulation layer 5 are respectively formed on the active region 1a. A gate pattern 6a is formed on a surface portion of the gate insulation layer 4. A first insulation pattern 7a is formed on the gate pattern 6a and a side wall spacer 8 is formed on each side of the gate insulation layer 4 and serves as a second insulation layer. The source 2 is formed of a low density impurity region 2a and a high density impurity region 2b, and the drain 3 is formed of a low density impurity region 3a and a high density impurity region 3b.
The fabrication process of the related art MOSFET will now be sequentially described with reference to FIGS. 2A through 2F. As shown in FIG. 2A, using a LOCOS method, an upper surface of semiconductor substrate 1 is defined into the active region 1a and the field region 1b. The gate insulation layer 4 is formed in the active region 1a and the field insulation layer 5 is formed in the field region, respectively, in an upper surface of a semiconductor substrate 1. A doped polysilicon layer is deposited on the gate and field insulation layers 4, 5 to serve as the gate 6, and a first insulation layer 7 is formed on the gate 6 using a CVD (Chemical Vapor Deposition) method.
As further shown in FIG. 2B, a photoresist pattern 9 is formed on the first insulation layer 7. Using the photoresist pattern 9 as a mask, the first insulation layer 7 is etched to expose a predetermined region thereof and form a first insulation pattern 7a. Referring to FIG. 2C, the photoresist pattern 9 is removed. The gate 6 is etched to expose a predetermined region of the gate insulation layer 4 and form a gate pattern 6a.
As shown in FIG. 2D, using the gate pattern 6a and the first insulation pattern 7a as a mask, lightly doped impurities are ion-implanted into the semiconductor substrate 1 to define portions of the source and drain 2a, 3a. An oxide material is formed on the respective upper surfaces of the gate insulation layer 4 and the field insulation layer 5 including the gate pattern 6a and the first insulation pattern 7a using a CVD method. The oxide material is etched-back for thereby forming a side wall spacer 8 on each side wall of the gate pattern 6a and the first insulation pattern 7a, and on a marginal upper surface of the gate insulation layer 4. At this time, the upper surface of the substrate 1 is partially exposed, and the low density impurity regions of the source and drain 2a, 3a are doped by n.sup.- or p.sup.-.
As shown in FIG. 2E, using the respective side wall spacers 8 as a mask, heavily doped impurities are ion-implanted into the exposed substrate 1. Accordingly, portions of the source and drain 2b, 3b that respectively serve as heavily doped impurity regions are defined to complete the related MOSFET fabrication. The heavily doped impurity regions 2b, 3b for the source and drain can be doped n.sup.+ or p.sup.+.
FIG. 3 shows a metallic wirework of a MOSFET having the structure of FIG. 1 further including a third insulation layer 10 formed on the exposed upper surface of the semiconductor substrate 1 including the field insulation layer 5, the side wall spacers 8, and the first insulation pattern 7a using a CVD method. A plurality of contact holes 11 are formed through the third insulation layer 10 to respectively expose upper surfaces of the gate pattern 6a and the source and drain regions 2b, 3b. A patterned metallic layer 12 is formed on the upper surface of the third insulation layer 10 including the contact holes 11.
As described above, the related art MOSFET has various disadvantages. The related art MOSFET is provided with a horizontal source and drain structure, so that the source and drain tend to occupy a considerable region on a semiconductor memory chip. Also, a fringing capacitor value increased because of a permitivity of the third insulation layer 10 formed between the gate 5 and the impurity regions 2, 3 operates to deteriorate a device characteristic and requires an isolation mask when forming the field region 1b. Such an isolation mask complicates a MOSFET fabrication process. Further, a junction depth becomes deepened when forming the source and drain 2b, 3b by ion-implanting heavily doped impurities and leads to a short channel effect.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.